Back planes of the prior art are exemplified in U.S. patent application Ser. No. 714,925, filed by Arnold F. Christiansen, Donald E. MacDonald, and George H. Wells, on Aug. 16, 1976, and assigned to Technology Marketing Incorporated, the disclosure of which is incorporated herein by reference. Such back planes typically have two layers of parallel conductor buses and pins connecting finger connectors to those buses via conductor pads. The finger connectors connect to circuit boards mounted edgewise on the back plane. One goal in the art has been to find an efficient way of connecting a plurality of processor circuit boards through separate memory interface boards to separate memory circuit boards. Another goal in the art has been to decrease the signal path length in the computer in order to increase the clock speed of the computer. Yet another goal in the art has been to use identical components such as memory interface circuit boards to reduce costs. However, use of prior art back planes such as the type disclosed in the above-referenced patent application has prevented the reduction of signal path lengths when a plurality of memories and a plurality of processors are interleaved and has prevented the use of identical memory interface circuit boards when the signal path lengths are minimized. Thus, the prior art has taught that there is no way to avoid an increase in path length with the addition of more memories and processors to be interleaved using back planes of the prior art. Furthermore, the prior art has taught that crossover of signal paths, which is well known to be undesirable in the art, cannot be avoided if identical memory interface circuit boards are used, thereby increasing the cost of interconnecting a plurality of processors and memories.